Array of IO in Xilinx constraints file [VHDL Spartan-6] -

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i'm learning program both vhdl , attempt implement on fpga (xilinx spartan-6 evaluation board). far have looked @ "getting started" guide here useless - shows me how great potential of fpga if know you're doing (which dont). i've watched youtube video make led blink through original vhdl code, constraint file , programming through impact/jtag.

so i've taken further , made button turns led on when held down has worked, of vector of led's turn on when press button, have declare pin locations each index, below;

net "led(0)" loc = "d17"; net "led(1)" loc = "ab4"; net "led(2)" loc = "d21"; net "led(3)" loc = "w15"; net "clk" loc = "k21"; net "button" loc = "f3";

how declare entire array of led(0) led(3) in 1 line? there must way given how large std_logic_vector can be.

as follow question, if knows of resources, tutorials, videos or books can me basics of programming spartan-6 (or equivalent) fpga novice level, massively appreciated!

many thanks!

david

xilinx ucf files support placeholders * , ?. unfortunately pin locations have no order or pattern can assign them 1 one.

our poc-library tries minimize end user work providing ready use ucf files meaningful signal names. it's possible load multiple ucf files 1 project.

here virtex-5 example. there xdc files vivado toolchain.


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