indexing - Choosing element from array in VHDL -

i have component receives array:

library ieee; use ieee.std_logic_1164.all;  use ieee.numeric_std.all; use work.index_pkg.all;  entity update_reg     port (     index         : in integer;     number_data   : in array_integer(9 downto 0);     output_number : out integer; ); end update_reg;  architecture behavior of update_reg begin process1 : process(index, number_data) begin     output_number <= number_data(index); end process;     end architecture; 

the purpose have @ component's output array's element specified index. built following tb test behaviour:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.index_pkg.all;   entity tb_update_reg end tb_update_reg;  architecture rtl of tb_update_reg  component update_reg     port (     index         : in integer;     number_data   : in array_integer(9 downto 0);     output_number : out integer ); end component;  signal tb_index         : integer; signal tb_number_data   : array_integer(9 downto 0); signal tb_output_number : integer;  begin fill_process : process(tb_number_data) begin     n in 0 9 loop         tb_number_data(n) <= 10 - n;     end loop; end process; stim_process : process begin     tb_index <= 6;     wait 2.0 ns;     tb_index <= 0;     wait 2.0 ns;     tb_index <= 9;     wait 2.0 ns;     tb_index <= 4;     wait 2.0 ns;     tb_index <= 1;     wait 2.0 ns; end process; upd_reg : update_reg port map(     index         => tb_index,     number_data   => tb_number_data,     output_number => tb_output_number ); end architecture; 

and added package included declaration array integer:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   package index_pkg      type array_integer array (natural range <>) of integer; end; 

i expect numbers 4/10/1/6/9. instead, simulation frozen. there aspect missing?

i grateful if help.

you have 2 issues:

i) need initialise signal tb_index 6:

signal tb_index         : integer := 6; 

in vhdl processes executed @ time 0 right @ start of simulation. without such initialisation, line in design:

output_number <= number_data(index); 

gets executed before index signal has been given value line:

tb_index <= 6; 

so, on first delta cycle value of index default integer, leftmost value (-2^31-1), of course out of range.

ii) need wait statement @ bottom of stim_process process:

    wait 2.0 ns;     wait; end process; 

in vhdl processes loop continuously. so, stim_process process loops top , simulation runs forever. wait; in vhdl means wait forever, need here.

also, line in design has semicolon:

output_number : out integer; 

it should be:

output_number : out integer 

http://www.edaplayground.com/x/3jan