synthesis - synthesizable FF in Verilog with active low reset -

i synthesize ff positive edge clock , active low reset. wrote following verilog code:

module dff_rstl (q,qn,clk,d, clearl); input  clk,d, clearl ; output q,qn; reg q; @(posedge clk or negedge clearl)            //asynchronous reset  begin     if (clearl) begin         q <= d;                  end  else    begin             q <= 1'b0;                     end          end assign  qn=~q; endmodule  

but following error during synthesis:

cannot test variable 'clearl' because not in event expression or wrong polarity. (elab-300) * presto compilation terminated 1 errors. *

do know can make synthesizable? lot!!!

the testing logic should ~clearl , first line/condition reset block .

module dff_rstl (q,qn,clk,d, clearl); input  clk,d, clearl ; output q,qn; reg q; @(posedge clk or negedge clearl)            //asynchronous reset  begin     if (~clearl) begin      q <= 1'b0;     end  else    begin         q <= d;    end end assign  qn=~q; endmodule